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A random scrambling of bits is likely to produce a different legal instruction. Doubling the size of the instruction encoding would enormously reduce the risk of a processor’s successfully executing a long enough sequence of unscrambled instructions to do damage. Although our preliminary analysis shows that this risk is low even with the current implementation, we believe that emerging softhardware architectures such as Crusoe [Klaiber 2000] will make it possible to reduce the risk even further.

This risk is much lower for the Power PC instruction set than it is for the IA32, due to the density of the IA32 instruction set. We thus conclude that a RISE approach would be even more successful on the Power PC architecture than it is on the IA32. As the complexity of systems grows, and 100% provable overall system security seems an ever more distant goal, the principle of diversity suggests that having a variety of defensive techniques based on different mechanisms with different properties stands to provide increased robustness, even if the techniques address partially or completely overlapping threats.

A. 2002. Improving the TCPA specification. IEEE Comput. ), 77–79. , AND GUPTA, D. 2004. Tied, libsafeplus: Tools for dynamic buffer overflow protection. In Proceeding of the 13th USENIX Security Symposium. San Diego, CA. AVIZIENIS, A. 1995. The methodology of N -version programming. In Software Fault Tolerance, M. Lyu, Ed. Wiley, New York, 23–46. AVIZIENIS, A. AND CHEN, L. 1977. On the implementation of N -Version programming for software fault tolerance during execution. In Proceedings of IEEE COMPSAC 77.

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ACM transactions on information and systems security (February) by D. R. Kuhn on corporate internet, B. Bertino on authorization constraints, V. Bhamidipati and others M. Nyanchama and S. Osborn on the role graph model, Ravi Sandhu


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