Communicating Process Architectures 2007: WoTUG-30 - download pdf or read online

By A. A. Mcewan

ISBN-10: 1586037676

ISBN-13: 9781586037673

This e-book offers with laptop technological know-how and types of Concurrency. It rather emphasises on hardware/software co-design, and the knowledge of concurrency that effects from those platforms. various papers in this subject were integrated, from the formal modeling of buses in co-design structures via to software program simulation and improvement environments. The ebook incorporates a contribution through Professor Sir Tony Hoare, the founder of the theoretical foundation upon which a lot of the paintings during this sequence relies. He stocks his new innovations on fine-grained concurrency. one other vital contribution is by way of Professor David might. He used to be leader architect for the Transputer and the occam programming language. The editors belief you can find this book informative and inspirational.

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Extra info for Communicating Process Architectures 2007: WoTUG-30

Example text

In SCOOP, a require clause on a routine belonging to a separate object specifies a wait condition: if the routine’s require clause evaluates to false, the processor associated with that object waits until the precondition is true before proceeding with routine execution. 5. Outline of CSP Model We constructed a model of SCOOP in CSP [4]. We initially chose CSP as our working language because of the existence of good tools (FDR2 and ProBE), and because the most interesting (and least understood) aspects of the problem at hand related to concurrency and synchronisation.

Communicating processes provide a natural way of expressing event-driven programs. Event-driven processes, triggered by communications, synchronisations and ports enable power to be minimised within a multicore. Clocked and timed ports allow the interface timing to be matched to external needs, decoupling on-chip operation from the interface. Programmed input-output rates can be sustained up to the process instruction rate. The interconnect architecture scales to hundreds of cores per chip. Inter-processor channels support over 100Mbytes in both directions simultaneously, and multiple concurrent channels between the processors support streaming applications.

As a result, the semantics of SCOOP is complicated, and understanding it would be easier with a formal model. We modelled SCOOP systems using CSP [3]; this model is presented in detail in [4]. The process of constructing the models, and identifying points of potential semantic variation, was informative: we found ambiguities and questions relating to lock passing and when locks should be released. Further, we desired to mechanically analyse the systems to compare and contrast different policies.

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Communicating Process Architectures 2007: WoTUG-30 by A. A. Mcewan


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